
MAX19711
10-Bit, 11Msps, Full-Duplex
Analog Front-End
24
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Rx ADC outputs AD0–AD9 are forced to tri-state. The
Tx DAC DA0–DA9 inputs are internally pulled to OVDD,
while the Tx DAC outputs are at 0V. The wake-up time
is 6.8s to enter Rx mode, 5s to enter Tx mode, and
6.8s to enter FD mode. When the Rx ADC outputs
transition from tri-state to active, the last converted
word is placed on the digital output bus.
In standby mode, the reference is powered but all other
device functions are off. The wake-up time from stand-
by mode is 7.2s to enter Rx mode, 21.8s to enter Tx
mode, and 21.8s to enter FD mode. When the Rx ADC
outputs transition from tri-state to active, the last con-
verted word is placed on the digital output bus.
FAST and SLOW Rx and Tx Modes
The MAX19711 features FAST and SLOW modes for
switching between Rx and Tx operation. In FAST Tx
mode, the Rx ADC core is powered on but the ADC digi-
tal outputs AD0–AD9 are tri-stated. The Tx DAC digital
bus is active and the DAC core is fully operational.
Table 10. Offset Control Bits for ID and QD Channels (IOFFSET or QOFFSET Mode)
BITS IO5–IO0 WHEN IN IOFFSET MODE, BITS QO5–QO0 WHEN IN QOFFSET MODE
IO5/QO5
IO4/QO4
IO3/QO3
IO2/QO2
IO1/QO1
IO0/QO0
OFFSET 1 LSB =
(VFSP-P / 1023)
1
-31 LSB
1
0
-30 LSB
1
0
1
-29 LSB
100
010
-2 LSB
100
001
-1 LSB
100
000
0mV
0
0mV (Default)
000
001
1 LSB
000
010
2 LSB
011
101
29 LSB
011
110
30 LSB
011
111
31 LSB
Note: For transmit full-scale select of ±410mV: 1 LSB = (820mVP-P / 1023) = 0.8016mV. For transmit full scale select of ±500mV: 1 LSB =
(1VP-P / 1023) = 0.9775mV.
Table 11. Common-Mode Select
(COMSEL Mode)
CM1
CM0
Tx PATH OUTPUT COMMON MODE (V)
0
1.36 (Default)
0
1
1.20
1
0
1.15
1
0.86
Table 12. WAKEUP-SEL Register
W2
W1
W0
POWER MODE AFTER WAKE-UP
(WAKE-UP STATE)
000
Invalid Value. This value is ignored
when inadvertently written to the
WAKEUP-SEL register.
0
1
IDLE
0
1
0
STBY
0
1
SPI1-SLOW Rx
1
0
SPI2-SLOW Tx
1
0
1
SPI3-FAST Rx
1
0
SPI4-FAST Tx
111
FD (Default)